UCLA Extension

High-Speed Digital Circuit Design and Applications

This course covers the electrical design principles associated with high speed digital PCB design and layout. It provides solutions to successfully handle the very fast edges, low noise margins, and other non-ideal characteristics of today’s digital devices including signal and power integrity-related system faults. The course begins with an introduction to today’s digital components and their characteristics. Topics include relative performance, noise margin, and interface requirements. The course then moves to system applications. System application topics include power distribution, signal interconnections, clock distribution, system initialization, memory device applications, and noise tolerant logic architectures. Power distribution topics includes means for calculating losses, the need for low-impedance planes and decoupling capacitors and their selection.Signal interconnection topics address line impedance, signal loading, crosstalk, transmission-line effects, noise tolerance, and worst-case timing. Included are some of the special requirements of GBit serial signal link interconnections.

Complete Details

Clock distribution topics include techniques for creating and distributing high-quality clock signals to components, boards, and systems. Memory device applications discusses some of the more common problems encountered with memory devices.

This course is designed for digital board design engineers, digital board layout designers, digital board test engineers and technicians, analog board designers, and power supply designers who use some digital components; anyone working with today’s high-speed digital circuits and who is interested in understanding how to design and build reliable, cost effective digital hardware. It can also be beneficial for managers and engineers who are interested in understanding the complexities of applying high-speed digital devices.

The course offers effective strategies for state-of-the-art high-speed digital PCB design and layout.

Strategies Include

  • noise-tolerant logic architectures
  • power distribution techniques that reduce noise
  • signal interconnection that control crosstalk and transmission-line effects
  • how to select interface devices with the proper noisy immunity
  • the special design issues that must be addresses when applying Gbit serial interconnections (SERDES)
  • clock distribution techniques that ensure clock signal quality
  • practical approaches to worst-case signal timing analysis
  • how to properly initialize a digital system
  • how to prevent upset (memory loss) of nonvolatile memory devices
  • how to avoid common memory design problems

Coordinator and Lecturer

Jim Buchanan, BSEE, high-speed digital design consultant, Minerva Engineering, Hanover, Maryland. Jim Buchanan has 45 years of experience in analog and digital design with Northrop Grumman Corp. Electronic Systems (ES) Division at Baltimore, Maryland. For approximately the last 20 years he has served as North Grumman Electronic Systems’ Digital Design Department’s principle design authority. During this time he conducted detailed electrical reviews of most of the circuit designs that originated in the Digital Design Department (which consisted of 150 to 200 designers during most of this period) and also served as a reviewer throughout Electronics Systems as well as other Northrop Grumman Divisions. His specialities include PC board and system signal and power integrity issues, mixed signal pc board and backplane design, and Gbit high-speed SERDES interconnection design. He is the author of numerous technical papers and three books on digital design. His books are CMOS/TTL Digital Systems Design, BiCMOS/CMOS Systems Design, and Signal and Power Integrity in Digital Systems all published by McGraw Hill. Jim is currently a high-speed digital design consultant on the staff of Minerva Engineering, Hanover, Maryland providing continued support to Northrop Grumman ES.

He has a BSEE from the University of Tennessee and a MSEE from the University of Maryland and is a registered Professional Engineer in the state of Maryland. He holds 18 patents. He is a recipient of the Northrop Grumman Electronic Systems’ Lifetime Achievement Award for Excellence in Engineering & Technology.

Daily Schedule

Day 1

Session 1–Introduction to high-speed logic devices: An overview of the relative performance and specifications, such as noise margin and operating speed, of various high-speed logic families are discussed. A number of tables are provided for comparison of characteristics. Circuit modeling techniques are introduced that aid in the understanding of logic circuit operation. The compatibility of various logic families and devices is discussed. Power sequencing concerns when different logic families are used on a common pc board or backplane are described and solutions are provided.

Session 2Power Distribution: The mechanisms that cause large internal device and load dependent transient switching currents and the detrimental effects of inductance in high-speed interconnection are discussed. Several examples show the possible magnitude of switching currents and demonstrate the possible adverse effects, such as ground bounce, that excessive inductance can cause. Guidance for minimizing inductance or the effects of inductance in power distribution systems is provided. The need for low-impedance power and ground distribution networks are discussed and the techniques for achieving them are described. Techniques for calculating losses in power distribution networks are described. Guidelines for the type, amount, and placement of decoupling capacitors and how they help compensate for losses in the power distribution system are provided.

Session 3Power Distribution (Cont.) and Signal Interconnections: The need for over-voltage protection on power inputs to digital hardware is described and means of providing that protection are shown. The many reasons for grounding digital hardware are discussed and proper techniques described. Signal interconnection topics include optimum line impedance and how to minimize crosstalk on pc boards, backplanes, connectors, and cables.

Session 4–Transmission-Line Effects and Clock Distribution: It is shown that transmission-line effects must be dealt with on almost all interconnections when today’s high-speed devices are used. Basic transmission-line theory and terminations are described along with termination methods compatible with digital device applications. The need for high-quality clock signals in high-speed systems and the techniques for distributing clock signals are described. It is stressed that a sound clock distribution scheme is one of the keys to a reliable high-speed digital system.

Day 2

Session 1Device, PC Board, and System Interfaces: Many of the practical interfacing issues that must be addressed at the device, pc board, and system levels are discussed. The importance of understanding the noise margin and common-mode operating range of interface devices is illustrated. The need to use differential devices with a large common-mode operating range or some form of devices with high noise immunity on unit-to-unit interfaces is discussed.

Session 2Gbit High-Speed Serial Interfaces (SERDES): Gbit SERDES signals have some very special interconnection design requirement that must be understood for their successful application. Some of these special requirements such as selection of pc board material and trace size and spacing to minimize signal loss as well as via and coupling capacitor pad design are discussed.

Session 3–Noise-Tolerant Logic Architectures and Worst-Case Timing: The noise tolerance of synchronous logic designs and the necessity for using synchronous design practices when high-speed logic devices are used is covered. Critical design issues for synchronous systems are described, such as techniques for synchronizing asynchronous signals and metastability and how to compensate for its effects. High-speed digital systems require a careful timing analysis of all signal paths to establish the maximum usable system clock frequency. Guidance for determining worst-case device and interconnection signal propagation delays is provided. A typical board-to.-board signal path is analyzed for worst-case signal propagation.

Session 4System Initialization and Memory Device Applications: Techniques for generating and distributing system initialization signals (commonly called reset signals) are described. Circuits used to generate initialization signals and their applications are covered. The need to protect reset or initialization signals from crosstalk or ground bounce are emphasized and means to do so are described. Write protection schemes for nonvolatile memory devices, such as EEPROMs, that prevent inadvertent writes during power ON or OFF switching or transients are covered. Many critical issues that are often overlooked when applying memory devices are discussed. The importance of in circuit memory component testing and the possible need for very complex test patterns is described.

For more information contact the Short Course Program Office:
shortcourses@uclaextension.edu | (310) 825-3344 | fax (310) 206-2815