UCLA Extension

Differential Signaling and Clock Distribution Control

This is one of five courses that comprise a week of instruction in high-speed digital design/EMI. Participants may take it on a stand-alone basis or in any combination with the other four courses:

Course Materials

Lecture notes are distributed on the day of the course. These notes are for participants only and are not for sale. Fee includes materials for each course(s) taken.

Coordinator and Lecturer

Robert Hanson, MSEE, President, Americom Seminars, Inc., Bremerton, Washington. Mr. Hanson has over 40 years of experience in the design manufacturing and test areas. His initial education was in industrial engineering (IE) and business administration. After receiving his BSEE/MSEE, he became highly involved in all aspects of electronic testing. As a digital design engineer at The Boeing Company, Rockwell, Honeywell, and Loral, Mr. Hanson designed and provided prototype operational analysis on many high-speed designs, including PCBs for AWACS, B1-B, 747-400, missiles, and ground support test equipment. He has played a very active role in automating the line, implemented robotics, participated in producibility studies, and automatic material handling. He has held positions responsible for overseeing and working in the CAE/CAD/CAT, JIT, simulation, and automatic assembly environments. He also has performed studies and headed research projects in the computer-integrated manufacturing environment. Mr. Hanson has extensive experience in the testing disciplines (both factory and field, commercial and military) and has been the testability overseer for Boeing Commercial Airline products.

Course Program

Differential Signaling

  • Attributes/drawbacks of loosely/tightly-coupled differential pairs
  • Definition and examples of differential and common mode V and I
  • Differential impedance: odd and even modes
  • Advantages and disadvantages of edge (side by side), broadside (dual), asymmetric, and microstrip differentials
  • Reflections and crosstalk in differentials; metastability, Clk skew, driver skew, bit pattern sensitivity, ISI, skin effect, and dielectric constant; jitter, BER, and the eye diagram
  • Matching electrical lengths

Clock Distribution

  • Timing margin and clock skew
  • Using low-impedance drivers and clock distribution lines
  • Source termination of multiple clock lines
  • Controlling crosstalk on clock lines
  • Delay adjustments: serpentine traces/DACs and varactors for dynamic delay
  • Differential distribution
  • Controlling clock signal duty cycle using the integrator
  • Source synchronous clocking, DDR and RDRAM

High-Speed Clocking

  • Clock skew and jitter
  • PLLs, DDLs, serpentine traces, and programmable delays
  • Source and end termination considerations for star, daisy chain, and driving multiple loads
  • Pre-emphasis and equalization techniques
  • The effects of ISI, skin, and dielectric losses
  • The effect of various base materials of long-haul transmission; the effects of eye closure on BER
  • A real-world example of compensation techniques

For more information contact the Short Course Program Office:
shortcourses@uclaextension.edu | (310) 825-3344 | fax (310) 206-2815