UCLA Extension

Crosstalk, Layer Stacking, Separating Analog/Digital Planes, and Terminations

This is one of five courses that comprise a week of instruction in high-speed digital design/EMI. Participants may take it on a stand-alone basis or in any combination with the other four courses:

Course Materials

Lecture notes are distributed on the day of the course. These notes are for participants only and are not for sale. Fee includes materials for each course(s) taken.

Coordinator and Lecturer

Robert Hanson, MSEE, President, Americom Seminars, Inc., Bremerton, Washington. Mr. Hanson has over 40 years of experience in the design manufacturing and test areas. His initial education was in industrial engineering (IE) and business administration. After receiving his BSEE/MSEE, he became highly involved in all aspects of electronic testing. As a digital design engineer at The Boeing Company, Rockwell, Honeywell, and Loral, Mr. Hanson designed and provided prototype operational analysis on many high-speed designs, including PCBs for AWACS, B1-B, 747-400, missiles, and ground support test equipment. He has played a very active role in automating the line, implemented robotics, participated in producibility studies, and automatic material handling. He has held positions responsible for overseeing and working in the CAE/CAD/CAT, JIT, simulation, and automatic assembly environments. He also has performed studies and headed research projects in the computer-integrated manufacturing environment. Mr. Hanson has extensive experience in the testing disciplines (both factory and field, commercial and military) and has been the testability overseer for Boeing Commercial Airline products.

Course Program

Ground Planes and Layer Stacking

  • High-speed current follows the path of least inductance
  • Crosstalk in solid and slotted ground planes
  • Inductive/capacitive ratios for micro strips, striplines, and asymmetric, dual, and edge differentials
  • Guard traces: do they stop crosstalk, can they resonate?
  • Near-end and far-end crosstalk
  • Separating analog from ECL/PECL and TTL/CMOS the concept of moats/floats/drawbridge
  • Split planes: CMOS/TTL, PECL, and analog using the same bias voltages
  • How to stack printed circuit board layers (e.g., 4, 6, and 10 layer) for Zo and crosstalk control, Cu fills on signal layers, minimizing warpage
  • Interplane capacitance: how thin, what material and stackup placement?
  • SIR vs. frequency, software for performing crosstalk and ground bounce tests


  • End/source/middle terminators
  • AC biasing for end terminators, where should it be used and how to choose the capacitor
  • Hairball networks, bifurcated lines, and capactive stubs
  • Terminating differentials: eliminating common mode and minimizing power
  • What causes differentials unbalance?
  • Diode and active terminators, resistor selection, and crosstalk in terminators

For more information contact the Short Course Program Office:
shortcourses@uclaextension.edu | (310) 825-3344 | fax (310) 206-2815