FPGAs for DSP and Software-Defined Radio
In this short course we will present, review, simulate then implement real-time DSP enabled software defined radios (SDR) on laptops, Raspberry Pis, Xilinx (Zynq) SoC FPGAs with RF transceivers. The design, simulation and implementation will take the form of a complete model based design work-flow from within MathWork’s MATLAB and Simulink software tools. The course will ensure attendees are educated in key relevant multi-rate DSP algorithms and techniques, in communications modulation methods, quadrature/QAM transceiver designs, and timing and synchronisation. The first part of the course will educate on DSP and communications, followed by a second part on FPGA systems implementation (focussing on Xilinx Zynq SoC) and introduce MathWorks Embedded and HDL Coder methods for hardware targeting. In the third and final part of the course we will develop real-time ‘desktop’ implementations of SDR transceivers using a model based design flow. We will start with floating point designs, which will evolve to fixed point, and then undergo final code generation stages with the Embedded and HDL Coder packages prior to FPGA deployment..
All attendees on the course will use (and take home!) an RTL-SDR device (which tunes from 25MHz to 1.75GHz) and have access to a Raspberry Pi and Zynq SDR kits in class hosting the RTL-SDR device and a wideband FMComms RF card respectively. The class format will be 40% lecture, 20% live SDR demonstration and 40% hands-on ‘desptop SDR’ using software and SDR hardware. Previous successful and hands-on versions of this course were given in March 2015 at the IEEE Vehicular Telecommunications Conference, in August 2015 at the IEEE Signal Processing and Education event in Utah, and also an IEEE Metro Workshop in October 2015 in the UK.
Attendees will receive notes, software licences, and hardware to take away after the course. The three volume custom set of notes comprises:
- DSP Theory and Communications Systems for SDR
- An introduction to FPGA Implementations and SDR model based design
- Software Defined Radio Design Workbook – Real RF signals, real radios, real fun!
In addition attendees will also take from 30 day licence versions of all of the software used on the course:
- A 30 day licence of MathWork’s MATLAB and Simulink software (including DSP Systems Toolbox, Signal Processing Toolbox, Communications System Toolbox, Embedded Coder & HDL Coder).
- Copies of the RTL-SDR, Zynq SDR, Zynq Embedded Coder and Raspberry Pi Hardware Support Packages for MATLAB and Simulink.
- A 30 day licence of the Xilinx Vivado software
- More than 120 SDR examples in MATLAB and Simulink and support materials on a USB memory stick.
- An RTL-SDR software defined radio (SDR) receiver (tunes over 20MHz to 1.7GHz).
Attendees can bring their own laptop (Linux, Mac or PC) for the class (PCs will of course also be provided as required) and the instructors will load 30 day evaluation versions of all of the software required for the duration of the course (this software can optionally be downloaded and installed prior to the course starting using full instructions we will provide). In addition to the RTL-SDR and Zynq SDR and Raspberry Pi SDR solutions, the course will also feature use of theUSRP, and picoZED SDR transceivers.
The presenters of this course are also the authors of the bestselling FPGA SoC book ‘The Zynq Book’, (2014, 450 pages, www.zynqbook.com) and also ‘Software Defined Radio using MATLAB & Simulink and the RTL-SDR’ (2015, 670 pages, www.desktopSDR.com). Note that PDF versions of both books can be freely downloaded from their websites, and are recommended background material for this course.
The following experience is required: basic programming/coding principles; electrical engineering principles; and bachelor’s or master’s degree-level mathematics. Previous experience with MATLAB and Simulink is useful, but not essential – first principles design materials will be available for those new to the software tools. Some background in DSP, as well as an awareness of HDL is useful but again not essential.
Who Should Attend
We would expect DSP and Communications Engineers, HDL designers, FPGAs engineers, RF engineers, and systems engineers.
Day 1 – Introduction to Digital Signal Processing for SDR
1. Some DSP, SDR and FPGA Fundamentals
- Sampling and Quantisation, ADCs and DACs
- DSP Fundamentals: z-notations and discrete systems
- Frequency domain analysis and DFT/FFT
- The Bandpass DSP System
- The Fundamental FPGA Architecture
- The generic Quadrature Amplitude Modulator (QAM) Transceiver
- DSP + FPGA + RF = SDR !
2. Digital FIR Filtering
- FIR filter design strategies
- Symmetric and half-band FIR filters
- Parallel, serial and multi-channel implementations
- Cut Set retiming techniques, and critical path / clock frequency
- Pipelining and latency consideration
- Cascade Integrate Comb (CIC) Filter Designs
3. Multirate DSP
- Oversampling systems
- Interpolation and decimation theory
- Direct and polyphase Interpolator and decimator architectures
- Undersampling and direct decimation methods
- Digital Up Converters (DUC) and Digital Down Converters (DDC)
- Cascading interpolating and decimation filters
4. Digital Communications
- Classic AM & FM modulation: transmit and receive
- Quadrature amplitude modulation (QAM) architectures
- Software Defined Radio (SDR): IF and RF architectures
- Complex modulation notation and spectral representation
- Digital modulation schemes (M-QAM, QPSK, 8-PSK etc.)
- Pulse shaping / Tx and Rx filters
5. Day 1: Hands-On Lab Examples:
- Getting Started with MATLAB and Simulink
- Live RF Spectrum Viewing with the RTL-SDR USB Radio Device
- Set up of in-lab (low power) AM and FM Transmitters on Zynq SDR
- Demonstration of in-lab (low power) AM and FM Transmitters on Zynq SDR
- Simulink model based design and implementation of an RTL-SDR AM Receiver at 433MHz
- Simulink model based design and implementation of an RTL-SDR FM Receiver at 102.5MHz
Day 2 – FPGAs and Model Based Design with HDL Coder and Code Generation
6. Fixed Point Arithmetic Review
- Number representations – floating point to fixed point
- Overflow and underflow / Rounding and quantisation
- Dynamic range, fractional wordlengths, and binary arithmetic
- The CORDIC algorithm: modes and calculations
7. FPGA Architectures
- FPGA interconnects and logics, slices, memory elements
- Resources for high speed Multiply-Accumulate based (DSP48’s)
- Zynq Architecture: Programmable Logic and Processors
- Mapping of DSP Algorithms to FPGA Architectures
8. Numerically Controlled Oscillators (NCOs) on FPGAs
- LUT (Lookup table) Methods for NCOs and CORDIC based NCOs
- Frequency precision and Spurious Free Dynamic Range (SFDR)
- Dithering and spur reduction techniques
- NCOs for QAM Radio Transmitters
9. Model Based Design
- Simulink DSP based Communications Transceiver designs
- Floating point simulation to Fixed point implementation
- HDL Coder Design Flow – from DSP Simulation to HDL Implementation
- Xilinx Vivado Implementation and Download to board
- Targetting Xilinx SDR ZedBoard
10. Day 2 Hands-On Lab Examples:
- Revisiting the Simulink model based design for the FM receiver — switching the RF front end from an RTL-SDR radio to a Zynq SDR radio (ZedBoard with an FMCOMMs front end)
- Performing Code Generation on the FM Receiver to deploy it to the Raspberry Pi (hosting an RTL-SDR radio)
- Using HDL Coder to target components of the FM Receiver to the Zynq FPGA (requires the Xilinx Vivado tools)
- Implementation of FM Receiver on Zynq SDR (ZedBoard with an FMCOMMs RF front end)
Day 3 – Software Defined Radio Designs
11. Frequency Tuning and Simple Synchronisation
- DSP/SDR methods for Selecting a Frequency Band: Tuning
- Spectral Representation for Complex Demodulation
- Frequency Offset Error and Correction at the Receiver
- Frequency Correction using a Complex Exponential
- Coherent Demodulation and Carrier Synchronisation
- Introduction to Phase Locked Loops
- Discrete Time PLL & Behaviours, Parameters and Characteristics
- Timing Errors, Symbol Recovery and Symbol Timing Synchronisation
- Digital Receiver Design: Joint Carrier and Timing Synchronisation
13. Desktop Digital Communications: QPSK Transmission and Reception
- Pulse Shaping with Real Time QPSK Transmitter and Receiver Designs
- Coarse Frequency Synchronisation in a Real-time System
- Carrier and Timing Synchronisation
- Data and Frame Synchronisation
- Transmitting Data, Audio and Images Across the Desktop on QAM Link
14. Day 3 Hands-On Lab Examples:
- Simulation of QPSK communications systems in Simulink Simulink model based design and implementation of RTL-SDR QPSK receiver with baseband carrier timing, phase and frame synchronization components
- Transmission of QPSK modulated images from Zynq SDR, to be acquired and demodulated by the RTL-SDR QPSK receiver Data in FM – Receiving data and images embedded in an FM audio signal
Coordinator and Lecturer
Robert W. Stewart, PhD , is the MathWorks Professor of Signal Processing at the University of Strathclyde (Glasgow, Scotland), Chair and Head of the Department of Electronic and Electrical Engineering, with more than 55 academic staff and almost 300 researchers. His recent research has been on digital communications and software defined radio, with specific interest in model based design and on radio standards such as LTE, 802.11. In 2015 Bob co-authored the open sourced book ‘Software Defined Radio using MATLAB/Simulink and RTL-SDR’ (www.desktopSDR.com). Bob was also the Director of the DSP and Communications company, Steepest Ascent Ltd, from 2004 to 2013. In 2013 the company was acquired by MathWorks who set up an office in Glasgow, Scotland. Bob has been a Visiting Professor at UCLA since 1997 when he first taught the Digital Signal Processing Theory and Algorithms Course, and then from 2002 to 2012 he taught the FPGAs for DSP and Communications course. Both courses were presented twice per year, and more than 1200 industry and academic attendees have attended since 1997.
Teaching Materials and Software Examples Development
Dr Louise Crockett is currently the Xilinx Academic Teaching Fellow in the Dept. of Electronic and Electrical Engineering (EEE), University of Strathclyde, UK. She graduated with MEng and PhD degrees in EEE in 2003 and 2008 respectively. Her technical and research interests are in DSP, digital communications, software defined radio, FPGA/ SoC based design and implementation, and professional education. She also teaches at undergraduate and MSc level on HDL, digital design, and FPGAs. Louise is the lead author of the Xilinx FPGA book, ‘The Zynq Book’, which has distributed more than 30,000 copies since 2014 (www.zynqbook.com) . Louise has specific expertise in HDL design flows and has developed the HDL SDR materials for the course and many of the SDR receiver designs.
For more information contact the Short Course Program Office:
firstname.lastname@example.org | (310) 825-3344 | fax (310) 206-2815