Design for Testability and for Built-In Self Test
Gain a comprehensive treatment of testability for all manifestations of electronics. The differences and commonalities of system-level, board-level, IC-level and core-level DFT will be explored, leading to a hierarchical solution. Learn some ad hoc approaches that are still useful for system-level and board-level testability. This course focuses on structured techniques that lend themselves to plan test better during the design stage. Explore the techniques that to provide built-in self-test (BIST) capabilities – not only at the IC level but also at the board and system levels as well.
The course discovers the need for a new paradigm, by which designs and tests are developed in parallel, resulting in earlier time to market, higher failure detection and lower test costs. It presents simple techniques to improve observability and controllability of any circuit. Designers can readily follow such guidelines. Moreover, the course examines structured scan techniques standardized by the IEEE-1149.1 (JTAG), by other IEEE-1149.x, by the IEEE-1500, the by the proposed IEEE-P1687 standards. A thorough understanding of these techniques for testability leads to similar BIST structures. The course covers memory BIST, logic BIST and analog BIST. Learn built-in test (BIT) software, and its goal to provide diagnostic information as well.
The course also teaches the need at system-level to provide repair instructions through module replacement. In order to achieve the unambiguous isolation of the faulty circuits testability has to be assessed at the design stage – often before the circuit details are known. Explore how this can be achieved using diagnostic assessment and modeling techniques. Finally, the course evaluates the value of DFT and BIST at all levels of assembly from an economic perspective. Attendees gain a thorough understanding of the techniques and also with the tools necessary to convince management that DFT and BIST will profit both manufacturing and support, while at the same time greatly improve the quality of units under test UUTs.
The course is primarily for designers and test engineers and provides great value to reliability, logistics, quality and manufacturing engineers as well. Managers concerned with testability and BIST techniques as well as those with general interest on IEEE and military standards in DFT also benefit from this course.
This course requires attendees to have an understanding of basic circuit elements such as logic gates, flip-flops and multiplexers.
Participants receive lecture notes on the first day of the course. These notes are for participants only and are not on sale.
Coordinator and Lecturer
Louis Y. Ungar, President of Advanced Test Engineering (A.T.E.) Solutions, Inc. El Segundo, CA. As a test engineer, Mr. Ungar designed automatic test equipment (ATE), created hundreds of test programs for dozens of ATEs. As a design engineer he designed payload systems for the Space Shuttle, eventually leading a team of designers. With both engineering and management experience in test and design, Mr. Ungar founded A.T.E. Solutions, Inc. in 1984, a highly respected test and testability consulting and educational firm.
Mr. Ungar serves as Testability Committee Chair for the Surface Mount Technology Association (SMTA), as Consultant to the American Society of Test Engineers (ASTE), the founding President of the Testability Management Action Group (TMAG) and various test and testability groups of the Institute of Electrical and Electronics Engineers (IEEE). He has recently balloted on the IEEE-1149.1-2013 and the IEEE-P1687. He can be reached at LouisUngar@ieee.org.
For more information contact the Short Course Program Office:
firstname.lastname@example.org | (310) 825-3344 | fax (310) 206-2815