UCLA Extension

Phase-Locked Loops for Digital Communications

A 2-Day Short Course

This course is designed for scientists, systems engineers, and software/hardware engineers desiring a comprehensive or refresher course on phase-locked loops (PLLs). Because many algorithms and architectures for modems are based upon PLLs, a solid understanding of the technology is essential to designing or analyzing high-performance communications systems.

Complete Details

The course begins with the traditional analysis techniques for PLLs, including partial fraction expansion, root locus, and Bode analysis. Real-time MATLAB and Mathematica simulations/analysis are embedded within the presentations and allow dynamic visualization of PLL operation and performance. Analog PLL theory and operation is presented on the first day and provides the foundation for the second day’s focus on digital phase-locked loops. Many practical implementations are actually hybrids, such as charge pumps, and these also are discussed in detail. Instruction also includes an introduction to optical phase-locked loops. A half-day laboratory provides participants with hands-on analysis and simulations of both digital and analog phase-locked loops.

Phase noise analysis of phase-locked loops and their components, such as digital dividers, are examined, along with measurement and mitigation techniques. (A specialty of the instructor is digital divider analysis.) Modern frequency synthesizer design, including both fractional-N and sigma-delta implementations, are reviewed and analyzed.

The course should enable participants to:

  • Compute first-, second-, and third-order PLL designs (both analog and digital implementations)
  • Perform root locus and bode stability analysis of analog and digital PLLs
  • Compute the nonlinear phase-plane trajectories and acquisition of analog and digital PLLs
  • Transform analog PLL designs to the digital domain
  • Design PLL charge pumps
  • Perform phase noise analysis of traditional and fractional PLLs and synthesizers

As part of the laboratory exercises, a set of MATLAB phase-locked loop models and simulations is provided. These models provide valuable insight into the design and operation of phase-locked loops and constitute a framework for the participants’ own designs.

This course provides the theoretical background for the follow-on course, Modem Design for Today’s Digital Communications, and although it is recommended that the two courses be taken in sequence, this is not a prerequisite.

Course Materials

The text, Phase-Locked Loops for Wireless Communications: Digital, Analog, and Optical Implementations, Second Edition, D.R. Stephens (Kluwer Academic Publishing, 2002), and lecture notes are distributed on the first day of the course. The notes are for participants only and are not for sale. A flashdrive containing laboratory exercises in MATLAB also is provided.

Coordinator and Lecturer

Donald R. Stephens, PhD, Chief Scientist, CommLargo, Inc., St. Petersburg, Florida. Dr. Stephens is a member of the JPEO JTRS technical staff. In addition to JTRS activities, he develops spectrally efficient waveforms for MILSATCOM and other military communication systems. To implement the waveform designs, he also develops novel modem architectures and algorithms exploiting communications theory and signal processing. With companies such as Raytheon, E-Systems, McDonnell Douglas, Emerson Electric, and Scientific Atlanta, he has developed multiple communications and radar receivers. These systems have included CPM, spread spectrum waveforms, wavelet video compression, and multi-spectral signal processing. Dr. Stephens also has participated in a joint government/industry MILSATCOM working group on Demand Assigned Multiple Access (DAMA). He is the author of the text, Phase-Locked Loops for Wireless Communications: Digital, Analog, and Optical Implementations, Second Edition (Kluwer Academic Publishing, 2002) and previously taught electromagnetic theory and digital signal processing as an adjunct professor at Southern Illinois University, Edwardsville.

Daily Schedule

Day 1

Introduction, interests, and applications. Introduction to phase-locked loops. Review of analog phase-locked loops, Laplace transform representations, linearized approximations, loop responses, stability analysis, loop noise bandwidth computation.

Nonlinear analysis of analog phase-locked loops, differential equations, Fokker-Planck analysis, acquisition analysis, cycle slips. Review of digital phase-locked loops. Transformations of analog loops. Review of digital transforms and loop analysis. Difference equations. Analysis of digital loop components.

Day 2

Digital PLL design and nonlinear digital PLL analysis. Acquisition and tracking performance. Noise bandwidth analysis of digital PLLs. Design of charge-pump PLLs. Introduction to optical PLLs. Fractional-N synthesizers. Phase noise analysis. Hands-on simulation and analysis of PLLs using MATLAB in the computer laboratory.

For more information contact the Short Course Program Office:
shortcourses@uclaextension.edu | (310) 825-3344 | fax (310) 206-2815

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