The speed of today’s logic devices creates PCB design challenges. If not designed correctly, you may be plagued with costly and time-consuming changes. Want the knowledge to design and layout a high-speed PCB correct the first time? This course helps you recognize problems with any proposed high-speed design, provides you with design rules and design processes to insure the PCB functions properly at the prototype stage, and emphasizes how to create a cost-competitive design without sacrificing high-speed integrity. Not an introductory course, our expert presents material at a technical level geared toward experienced designers.
Switching edges are in the 200ps to 300ps range and some devices have edges that have broken the 50ps barrier. This has resulted in high-speed design problems such as:
- A lack of control over impedance and reflections
- Crosstalk and bypassing failures
- Time delays, false triggering and reflections
- Failure to meet EMI and FCC requirements
It is the edge rate, not the frequency, which exacerbates this problem. So, even if your design is for moderate frequency, the edge rates can cause these designs to reflect the high-speed effects.
Most designs today use a microprocessor and today’s micros have clock rates about 400 times higher than the original 8 and 16 bit machines. A key factor is the minimization of the semiconductor device (now at 10 nm) leading to less parasitic L and C and thereby faster switching rates. This phenomenon is also apparent in RAMs, ROMs, ASICs and Gate Arrays. This leads to PCBs requiring terminators, new CAD routing disciplines, and component additions to minimize ground bounce effects. More and more designs are requiring these faster devices to meet more demanding specifications that match or beat the competition.
The course provides you with the knowledge to do it right the first time. The course provides tools for recognizing the problems with any proposed high-speed design. Design rules and design processes are taught that insure the PCB will function properly at the prototype stage. The course emphasizes cost competitive design without sacrificing high-speed integrity.
This course is for anyone who has worked with today’s ICs, high-speed designs and PCB layouts. No advanced math is required though attendees will find it helpful to bring a scientific calculator to the course. The course is not an introductory course. It is presented at a technical level that will provide experienced designers with information to design and layout a high speed PCB.
Who Should Attend: Digital logic engineers, system architects, technicians, PCB layout professionals, IC designers, IC package designers, application engineers, anyone who works with high-speed digital logic, anyone who works with any logic implemented in the submicron processes that are becoming standard in the industry, engineering managers, and project managers.
Coordinator & Lecturer:
Robert Hanson, MSEE, has unmatched experience in teaching and knowledge of electronics. As a Testability Overseer for Boeing CommercialAirline products, Mr. Hanson has worked with non-EEs and EEs. He understands the need to use clear communication,and he spends extra time answering student questions during his presentations or privately afterward. Mr. Hanson has over 40 years of experience in the design manufacturing and testing areas. His initial education was in Industrial Engineering (BSIE) Business Administration (BSBA). After receiving his BSEE/MSEE, he became highly involved in all aspects of electronic testing. As a digital design engineer at The Boeing Company, Rockwell, Honeywell, and Loral.
Mr. Hanson designed and provided prototype operational analysis on many high-speed designs, including PCBs for AWACs, B1-B, 747-400, missiles, and ground support test equipment. He has played a very active role in automating the line,implementing robotics, and participating in producibility studies and working in the CAE/CAD/CAT, JIT,simulation,and automatic assembly environments. He has also performed studies and headed research projects in the computer-integrated manufacturing environment. Mr. Hanson has extensive experience in the testing disciplines (both factory and field,commerical and military as the testability overseer for Boeing Commercial Airline products.
Building on that practical knowledge, Mr. Hanson has taught these courses many times receiving outstanding reviews each time from participants. He has presented his courses for the University of California – Berkeley, University of Wisconsin, University of Oxford (England), Seattle Pacific University, University of Washington, University of California – Los Angeles. Mr. Hanson has taught electronic courses throughout the United States, Europe,South Africa,the Middle East, and Asia.
AWARDS : Boeing Company Aerospace Man of the Year for saving $6,000,000 for inventing a new testing technique for the Boeing B-1 bomber electronics.
Robert Hanson has conducted private seminars and/or consulting for 3-Com, Advanced Fibre Communications, Alcatel, Allied Signal,AMO, AMO-Dresden,Apple, AT&T,Autoliv, Boeing, Chrysler, Cisco, Compaq, Cray, da Vinci Systems, Data Device, Dell, Delphi, EDA Technologies – South Africa, Ford, Free Scale Technologies, Gateway , GE, GenRad, Honeywell, HP, HP – Barcelona, IBM, Intel, Kaneta High Tech Materials, KLA Tencor, Lockheed, Lucent, LXE, Marconi, Micron, Motorola, NASA, NEC,eLuminant, Navico, Nortel,Northrop Grumman, Panasonic, Qualcomm, Raytheon, Rockwell, Samsung-Korea,Solectron, Storage Tek,Sun, Tektronix, Teradyne,Texas Instruments,TRW, Tyco Electronics,Tycom Laboratories, U.S. Trade Commission, United Defense, Wilson-Sonsini-Goodrich and roseti Law Firm, Xerox,and Xilinx.
ABT Media – Singapore,Advanced Electronic Diagnosis (AED) – Saudi Arabia,Atkins Technical, Inc., Bacharach Inc. BBN Graphics, Benthos,Bourns, Compression Labs, Inc. Con Med Linvatec, Goutier, Delphax, Dynalco, Eldec, First Inertial Switch, Fluke,Genicom, Hathaway,Johnson&Johnson,Jet Propulsion Labs (JPL), Loral Aerospace , Martin Marietta, Maxim Integrated Products,McBeth, Medrad, Medtronic, Motion Engineering, Inc., Norsat lnternatinal,Okidata, Pharmacia Deltec, Precor,Satcom,Southern Research Institute,Wellex, Aesalsan (Turkey),Jefferson Labs,Schmitt, NVE, McDermott,Will, and Emery Law Firm, FLIR, Data 1/0, Pulsecom,Symbol Technologies, U.S. Navy – Idaho, and JSI.
- Frequency, Time and Distance
- Lumped Versus Distributed Systems
- EM Fields
- Geometry, C, L, & Zo, interrelationships
- C & L Resonance
High-Speed Properties of Logic Gates
- Quiescent vs. Active Dissipation
- Driving Capacitive Loads
- Input Power and External Power
- TTL, CMOS, SiGe, In Pn, ECL, & GaAs; Output Power, Speed and engineering disciplines, Dv, di effects and Voltage Margins
- Low K Di-electrics
- Intersymbol Interference (ISI), eye diagrams and jitter
- Shoot Through Current (SSO) and how to minimize it
- Ground Bounce, Lead Inductance, Simultaneous Switching Noise (SSN)
- Rise Time and Bandwidth of Oscilloscopes and probes
- Self-inductance and Spurious Signal Pickup of a Probe Ground Loop
- Viewing a Serial Data Transmission System, the eye pattern closure ISI, Skin effect and tan loss.
- PLL and DLLs
- Effects of Source and Load Impedance
- Special Transmission Line Cases
- Determining Line Impedance & Propagation Delay using TDR
- Skin/proximity effect & Dielectric Loss
- Defining S parameters and how to use them
- The Capacitive Load – Zo and propagation delay
- Matching Z0 with trace alturations (neckdowns) – minimizing the
- C load
- 900, 450 bends – are they concerns?
- Characteristics impedance & propagation delay for all Transmission Line configurations
- End/Source/Middle Terminators
- AC Biasing for End Terminators, where should it be used and how to choose the capacitor
- Hairball networks, bifurcated lines and capactive stubs
- Terminating differentials – Eliminating common mode and minimizing power
- What causes differentials unbalance?
- Diode and active terminators, Resistor Selection and Crosstalk in Terminators
- Capacitance & Inductance of Vias
- Return Current and Its Relation to Vias
- Through Hole, Blind, Buried, Micro Vias
- Intelligent Vias and autorouters
- Via discontinuity and via resonance concerns
- Ground Planes and Layer Stacking
- High-Speed Current Follows the Path of Least Inductance
- Crosstalk in Solid and Slotted Ground Planes
- Inductive/capacitive ratios for micro strips, striplines, and asymmetric, dual, and edge LVDS
- Guard Traces – Do they stop crosstalk, can they resonate?
- Near-End and Far-End Crosstalk
- Separating analog from ECL/PECL and TTL/CMOS the concept of moats/floats/drawbridge
- Split planes – CMOS/TTL, PECL and analog using the same bias voltages
- How to Stack Printed Circuit Board Layers (e.g. 4, 6, and 10 layer) for Zo and crosstalk control, Cu fills on signal layers, minimizing warpage
- Interplane Capacitance – How thin, what material and stackup placement
- Power Systems
- Providing a stable Voltage Reference – Cu planes
- Distributing Uniform Voltage – Sense lines, bulk C and interplane C
- Choosing a Bypass Capacitor – Electrolytic/tantalum and ceramic
- Power plane resonance – serial and parallel, how to minimize both
- Designing a .1 ohm bypass system up to Fknee
- Designing for constant ESR
- IC die capacitance, discrete C in the IC package
- Why the 0201 – Both for better bypassing and EMI control
- Minimizing inductance/capacitance layouts for SOICs, PLCCs, and various configurations of BGAs.
- Connectors & Cables
- Mutual and Series Inductance – How Connectors Create Crosstalk
- and EMI
- Using Connectors on a Multidrop Bus (Z mismatch reflection) and how to match Zc to Zo,
- Measuring Coupling in a Connector
- Continuity of Gnd Underneath a Connector
- Special Connectors for High-Speed requirements – Crosstalk and matching Zo
- Differential Signaling Through a Connector
- Multidrop systems: Drivers and Transceivers.
- How they function, Clock rates, typical failures
- ISI – Minimize the effect with Equalization and Preemphasis
- LVDS: types, unbalance, noise, layout & making them function
- Methods to speed up busses – Distributive driving and load capacitance matching
- Timing Margin and Clock Skew
- Using Low-Impedance Drivers and Clock Distribution Lines
- Controlling Crosstalk on Clock Lines
- Delay Adjustments – Serpentine traces
- Controlling Clock Signal Duty Cycle using the integrator
- Differential Signaling
- Attributes/drawbacks of loosely/tightly coupled differential pairs
- Definition and examples of differential and common mode V and I
- Differential impedance: odd and even modes
- Advantages and disadvantages of edge (side by side), broadside (dual), asymmetric, and microstrip differentials
- Reflections and crosstalk in differentials; metastability, Clock skew, driver skew, bit pattern sensitivity, ISI, skin effect, and dielectric constant; jitter, BER, and the eye diagram
- Matching electrical lengths
Each Student Receives
- A 223-page comprehensive set of course notes.
- Text: “High-Speed Digital Design: A Handbook of Black Magic,” by Howard Johnson, Ph. D. and Martin Graham, Ph.D.
- A 26-page “How to Become a Circuit Master,” a booklet which provides a detailed description of how a bareboard is manufactured and tested.
A supplemental addendum reinforcing information in the course notes is included.
For more information contact the Short Course Program Office:
firstname.lastname@example.org | (310) 825-3344 | fax (310) 206-2815