UCLA Extension

Bypassing, Power Delivery, Vias, Connectors, and Buses

This is one of five courses that comprise a week of instruction in high-speed digital design/EMI. Participants may take it on a stand-alone basis or in any combination with the other four courses:

Course Materials

Lecture notes are distributed on the day of the course. These notes are for participants only and are not for sale. Fee includes materials for each course(s) taken.

Coordinator and Lecturer

Robert Hanson, MSEE, President, Americom Seminars, Inc., Bremerton, Washington. Mr. Hanson has over 40 years of experience in the design manufacturing and test areas. His initial education was in industrial engineering (IE) and business administration. After receiving his BSEE/MSEE, he became highly involved in all aspects of electronic testing. As a digital design engineer at The Boeing Company, Rockwell, Honeywell, and Loral, Mr. Hanson designed and provided prototype operational analysis on many high-speed designs, including PCBs for AWACS, B1-B, 747-400, missiles, and ground support test equipment. He has played a very active role in automating the line, implemented robotics, participated in producibility studies, and automatic material handling. He has held positions responsible for overseeing and working in the CAE/CAD/CAT, JIT, simulation, and automatic assembly environments. He also has performed studies and headed research projects in the computer-integrated manufacturing environment. Mr. Hanson has extensive experience in the testing disciplines (both factory and field, commercial and military) and has been the testability overseer for Boeing Commercial Airline products.

Course Program

Power Systems

  • Providing a stable voltage reference: Cu planes
  • Distributing uniform voltage: sense lines, bulk C, and interplane C
  • Choosing a bypass capacitor: electrolytic/tantalum and ceramic
  • Power plane resonance: serial and parallel, how to minimize both
  • Designing a .1 ohm bypass system up to Fknee
  • Designing for constant ESR
  • IC die capacitance, discrete C in the IC package
  • Why the 0201: both for better bypassing and EMI control
  • Minimizing L-capacitor layouts for SOICs, PLCCs, and various configurations of BGAs
  • Layout requirements for power delivery

Vias

  • Mechanical properties of vias
  • Capacitance and inductance of vias
  • Return current and its relation to vias
  • Through hole, blind, buried, micro vias
  • Intelligent vias and autorouters
  • Via discontinuity and via resonance concerns

Connectors and Cables

  • Mutual and series inductance: how connectors create crosstalk and EMI
  • Using connectors on a multidrop bus (Z mismatch reflection) and how to match Zc to Zo
  • Measuring coupling in a connector
  • Continuity of Gnd underneath a connector
  • Special connectors for high-speed requirements: crosstalk and matching Zo
  • Matching signaling through a connector (impedance discontinuity)

Buses

  • Multidrop systems: drivers, transceivers, and designing a high-speed bus
  • How they function, clock rates, typical failures
  • ISI: minimize the effect with equalization and preemphasis
  • LVDS: types, unbalance, noise, layout, and making them function
  • Methods to speed up busses: distributive driving and load capacitance matching

For more information contact the Short Course Program Office:
shortcourses@uclaextension.edu | (310) 825-3344 | fax (310) 206-2815

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