February 18 – 20, 2020
The speed of today’s logic devices mandates that the interconnects on PCBs must meet the high switching rise/fall times of these devices. Switching edges are in the 200ps to 300ps range and some devices have edges that have broken the 50ps barrier. This has resulted in high-speed design problems such as a lack of control over impedance and reflections; crosstalk, bypassing, and power delivery failures; time delays, false triggering and reflections; and failure to meet EMI and FCC requirements. It is the edge rate, not the frequency, which exacerbates this problem. So, even if your design is for moderate frequency, the edge rates can cause these designs to reflect the high-speed effects. Most designs today use a microprocessor and today’s micros have clock rates about 400 times higher than the original 8 and 16 bit machines. A key factor is the minimization of the semiconductor device (now at 20 nm with the FINFETS) leading to less parasitic L and C and thereby faster switching rates. This phenomenon is also apparent in RAMs, ROMs, ASICs and Gate Arrays. This leads to PCBs requiring terminators, new CAD routing disciplines, and component additions to minimize ground bounce effects. More and more designs are requiring these faster devices to meet more demanding specifications that match or beat the competition. The course provides you with the knowledge to do it right the first time. The course provides tools for recognizing the problems with any proposed high-speed design. Design rules and design processes are taught that insure the PCB will function properly at the prototype stage. The course emphasizes cost competitive design without sacrificing high-speed integrity.
Coordinator and Lecturer
Robert Hanson, MSEE has unmatched experience in teaching and knowledge of electronics. As a Testability Overseer for Boeing Commercial Airline products, Mr. Hanson has worked with non-EEs and EE’s. He understands the need to use clear communication and he spends extra time answering student questions during his presentations or privately afterward.
Mr. Hanson has over 40 years of experience in the design manufacturing and testing areas. His initial education was in (BSIE) and Business Administration (BSBA). After receiving his BSEE/MSEE, he became highly involved in all aspects of electronic testing. As a digital design engineer at The Boeing Company, Rockwell, Honeywell, and LoraL, Mr. Hanson designed and provided prototype operational analysis on many high-speed designs, including PCBs for AWACS, B1-B, 747-400, missiles, and ground support test equipment. He has played a very active role in automating the line, implementing robotics, and participating in producibility studies and working in the CAE/CAD/CAT, JIT, simulation, and automatic assembly environments. He also has performed studies and headed research projects in the computer-integrated manufacturing environment. Mr. Hanson has extensive experience in the testing disciplines (both factory and field, commercial and military as the testability overseer for Boeing Commercial Airline products.
Building on that practical knowledge, Mr. Hanson has taught these courses many times receiving outstanding reviews each time from participants. He has presented his courses for the University of California at Berkeley, University of Wisconsin, University of Oxford (England), Seattle Pacific University, University of Washington, and most recently he teaches several classes for University of California- Los Angeles as well as for over 100 private companies on-site. His clear instruction builds on 40 years of working experience in electronics including in manufacturing, hardware testing, and operational/test software. His teaching also reflects the fact that he has taught electronics courses throughout the United States, Europe, South Africa, the Middle East, and Asia. Mr. Hanson has an M.S.E.E. from the University of Southern California, a B.S.E.E. from the University of Washington, and a B.S.I.E. and a B.S.B.A. from the University of North Dakota. He brings his practical experience and educational background to present a seminar that both EEs and non-EEs will find accessible and useful.
AWARDS: Boeing Company Aerospace Man of the Year for saving $6,000,000 for inventing a new testing technique for the Boeing B-1 bomber electronics.
Robert Hanson has conducted private seminars and/or consulting for 3-Com, Advanced Fibre Communications, Alcatel, Allied Signal, AMD, AMD-Dresden, Apple, AT&T, Autoliv, Boeing, Chrysler, Cisco, Compaq, Cray, da Vinci Systems, Data Device, Dell, Delphi, EDA Technologies-So. Africa, Ford, Freescale Technologies, Gateway, GE, Gen Rad, Honeywell, HP, IBM, Intel, Kaneta High Tech Materials, KLA Tencor, Lockheed, Lucent, LXE, Marconi, Micron, Motorola, NASA, NEC, eLuminant, Navico, Nortel, Northrop Grumman, Panasonic, Qualcomm, Raytheon, Rockwell, Samsung-Korea, Solectron, Storage Tek, Sun, Tektronix, Teradyne, Texas Instruments, TRW, Tyco Electronics, Tycom Laboratories, U.S. Trade Commission, United Defense, Wilson-Sonsini-Goodrich and Roseti Law Firm, Xerox, and Xilinx. AND ABT Media – Singapore, Autoliv, Advanced Electronic Diagnosis (AED) Saudi Arabia, Atkins Tehcnical, Inc., Bacharach, Inc., BBN Graphics, Benthos, Bourns, Compression Labs, Inc., ConMed Linvatec – California, Coulter, Dalphax, Dynalco, NASA-Edwards AFB, Hewlett Packard – Barcelona, Eldec, First Inertial Switch, Fluke, Genicom, Hathaway, Johnson & Johnson, Jet Propulsion Labs (JPL), Loral Aerospace, Martin Marietta, McBeth, Medrad, Medtronic, Motion Engineering, Inc., Norsat International, Okidata, Pharmacia Deltec, Precor, Satcom, Southern Research Institute, Wellex, Jefferson Labs, Aselsan (Turkey), Schmitt, NVE, Mc Dermott, Will, and Emery Law Firm, FLIR, Data I/O, Pulsecom, Symbol Technologies, U.S. Navy – Idaho, and JSI.
This course is for anyone who has worked with today’s ICs, high-speed designs and PCB layouts. No advanced math is required though attendees will find it helpful to bring a scientific calculator to the course. The course is not an introductory course. It is presented at a technical level that will provide experienced designers with information to design and layout a high speed PCB.
- Frequency, time, and distance
- Lumped vs. distributed systems
- 4 kinds of reactance
- Ordinary and mutual capacitance and inductance
- EM fields
- Geometry, C, L, and Zo, interrelationships
- C&L resonance
High-Speed Properties of Logic Gates
- Quiescent vs. active dissipation
- Driving capacitive loads
- Input power and external power
- TTL, CMOS, SiGe, In Pn, ECL, and GaAs
- Output power, speed and engineering disciplines
- Dv, di effects, and voltage margins
- ICs: Cu vs. Al; what are the issues?
- Low K dielectrics
- Intersymbol Interference (ISI), eye diagrams, and jitter
- Shoot Through Current (SSO) and how to minimize it
- Ground bounce, lead inductance, and Simultaneous Switching Noise (SSN)
- Lead Capacitance and Thermal Considerations
- Rise time and bandwidth of oscilloscopes and probes
- Self-inductance and spurious signal pickup of a probe ground loop
- How probes load down a circuit
- Special probing fixtures
- Avoiding pickup from probe shield currents
- Viewing a serial data transmission system, the eye pattern closure: ISI, skin effect, and tan loss
- PLL and DLLs
- Slowing down the system clock
- Observing crosstalk
- Measuring operating margins
- Observing metastable states in flip-flops
- Infinite uniform transmission line
- Effects of source and load impedance
- Special transmission line cases
- Determining line impedance and propagation delay using TDR and VNA
- Skin/proximity effect and dielectric loss
- Definition and use of S parameters
- The capacitive load: Zo and propagation delay
- Matching Zo with trace alturations (neckdowns): minimizing the C load
- 90° and 45° bends: are they concerns?
- Characteristics of T lines: coax, pair, micro strip, buried micro strip, stripline, and differential: asymmetric, dual, and edge
- Even/odd and differential/common modes and their effects on LVDS
- End/source/middle terminators
- AC biasing for end terminators: where should it be used and how to choose the capacitor
- Hairball networks, bifurcated lines, and capactive stubs
- Terminating differentials: eliminating common mode and minimizing power
- What causes differentials unbalance?
- Diode and active terminators, resistor selection, and crosstalk in terminators
- Mechanical properties of vias
- Capacitance and inductance of vias
- Return current and its relation to vias
- Through hole, blind, buried, and micro vias
- Intelligent vias and autorouters
- Via discontinuity and via resonance concerns
Ground Planes and Layer Stacking
- High-speed current follows the path of least inductance
- Crosstalk in solid and slotted ground planes
- Inductive/capacitive ratios for micro strips, striplines, and asymmetric, dual, and edge LVDS
- Guard traces: do they stop crosstalk and can they resonate?
- Near-end and far-end crosstalk
- Separating analog from ECL/PECL, and TTL/CMOS the concept of moats/floats/drawbridge
- Split planes: CMOS/TTL, PECL, and analog using the same bias voltages
- How to stack printed circuit board layers (e.g., 4, 6, and 10 layer) for Zo and crosstalk control, Cu fills on signal layers, and minimizing warpage
- Interplane capacitance: how thin, what material, and stackup placement
- Providing a stable voltage reference: Cu planes
- Distributing uniform voltage: sense lines, bulk C, and interplane C
- Choosing a bypass capacitor: electrolytic/tantalum and ceramic
- Power plane resonance: serial and parallel; how to minimize both
- Designing a .1 ohm bypass system up to Fknee
- Designing for constant ESR. IC die capacitance; discrete C in the IC package
- Why the 0201–both for better bypassing and EMI control
- Minimizing L-capacitor layouts for SOICs, PLCCs, and various configurations of BGAs
Connectors, Cables and Buses
- Mutual and Series Inductance – How Connectors Create Crosstalk
- Using Connectors on a Multidrop Bus (Z mismatch reflection) and how to match Zc to Zo,
- Measuring Coupling in a Connector
- Continuity of Gnd Underneath a Connector
- Special Connectors for High-Speed requirements – Crosstalk and matching Zo
- Differential Signaling Through a Connector
- Multidrop systems: Drivers, Transceivers & RAMBUS techniques
- How they function, Clock rates, typical failures
- ISI – Minimize the effect with Equalization and Pre-emphasis, DFE and CTLE
- LVDS: types, unbalance, noise, layout & making them function
- Methods to speed up busses – Distributive driving and load capacitance matching
- PAM4, Pre-emphasis, equalization, CTLE, and DFE
- Timing Margin and Clock Skew
- Using Low-Impedance Drivers and Clock Distribution Lines
- Source Termination of Multiple Clock Lines
- Controlling Crosstalk on Clock Lines
- Delay Adjustments – Serpentine traces/DACs and varisters for dynamic delay
- Differential Distribution
- Attributes/drawbacks of loosely/tightly coupled differential pairs
- Definition and examples of differential and common mode V and I
- Differential impedance: odd and even modes
- Advantages and disadvantages of edge (side by side), broadside (dual), asymmetric, and microstrip differentials
- Reflections and crosstalk in differentials; metastability, Clk skew, driver skew, bit pattern sensitivity, ISI, skin effect, and dielectric constant; jitter, BER, and the eye diagram
- Matching electrical lengths
Each student will receive the following:
- A 304-page supplemental course notes
- Source Textbook: “High-Speed Digital Design: A Handbook of Black Magic” by Howard Johnson, PhD and Martin Graham, PhD.
- A 31-page addendum (analysis, high speed & EMI design guides)
- Bareboard considerations using mechanically spread glass for designing 5G PCBs running at 27 Gb/s data rates.
During the course PCBs, laminates, ICs, etc. will be shown to emphasize and provide clarity to the subject being discussed.
For more information contact the Short Course Program Office:
firstname.lastname@example.org | (310) 825-3344 | fax (310) 206-2815