UCLA Extension

High-Speed Digital Design and PCB Layout

The speed of today’s logic devices mandates that the interconnects on PCBs must meet the high switching rise/fall times of these devices. Switching edges are in the 200ps to 300ps range and some devices have edges that have reached the 17ps barrier. This has resulted in high-speed design problems. Even if a design is for moderate frequency, the edge rates can cause it to reflect the high-speed effects.

This course provides participants with the tools for recognizing the problems with any proposed high-speed design. Students learn design rules and design processes that insure the PCB will function properly at the prototype stage. Instruction emphasizes cost-competitive design without sacrificing high-speed integrity.

The course benefits digital design engineers, design managers, test engineers, EMI/EMC engineers, IC digital logic designers, project managers of high-speed designs, communication engineers, and military digital engineers. No advanced math is required, although participants will find it helpful to bring a scientific calculator to the course. Instruction presents course material at a technical level that provides experienced designers with information to design and lay out a high-speed PCB that meets signal integrity (SI) and EMI.

Course Materials

Participants receive the text High-Speed Digital Design, Howard Johnson and Martin Graham (Prentice-Hall, 1993) and lecture notes on the first day of the course. The notes are for participants only and are not for sale.

Coordinator and Lecturer

Robert Hanson, MSEE, President, Americom Seminars, Inc., Bremerton, Washington. Mr. Hanson has over 40 years of experience in the design manufacturing and test areas. His initial education was in industrial engineering and business administration. After receiving his BSEE/MSEE, he became highly involved in all aspects of electronic testing. As a digital design engineer at The Boeing Company, Rockwell, Honeywell, and Loral, Mr. Hanson designed and provided prototype operational analysis on many high-speed designs, including PCBs for AWACS, B1-B, 747-400, missiles, and ground support test equipment. He has played a very active role in automating the line, implemented robotics, and participated in producibility studies and automatic material handling. He has held positions responsible for overseeing and working in the CAE/CAD/CAT, JIT, simulation, and automatic assembly environments. He also has performed studies and headed research projects in the computer-integrated manufacturing environment. Mr. Hanson has extensive experience in the testing disciplines (both factory and field, commercial and military) and has been the testability overseer for Boeing Commercial Airline products.

Program

Fundamentals

  • Frequency, time, and distance
  • Lumped vs. distributed systems
  • 4 kinds of reactance
  • Ordinary and mutual capacitance and inductance
  • EM fields
  • Geometry, C, L, and ZO, interrelationships
  • C&L resonance

High-Speed Properties of Logic Gates

  • Quiescent vs. active dissipation
  • Driving capacitive loads
  • Input power and external power
  • TTL, CMOS, SiGe, In Pn, ECL, and GaAs
  • Output power, speed and engineering disciplines
  • Dv, di effects, and voltage margins
  • ICs: Cu vs. Al; what are the issues?
  • Low K dielectrics
  • Intersymbol Interference (ISI), eye diagrams, and jitter
  • Shoot Through Current (SSO) and how to minimize it
  • Ground bounce, lead inductance, and Simultaneous Switching Noise (SSN)
  • Electronic packages: QFPs, PGAs, SOIC, PLCC, BGA, COB, TAB, FC, CSP, and their relationship to SI lead capacitance and thermal considerations

Measurement Techniques

  • Rise time and bandwidth of oscilloscopes and probes
  • Self-inductance and spurious signal pickup of a probe ground loop
  • How probes load down a circuit
  • Special probing fixtures
  • Avoiding pickup from probe shield currents
  • Viewing a serial data transmission system, the eye pattern closure: ISI, skin effect, and tan loss
  • PLL and DLLs. Communications: SONET, SERDES, OC 192/768, fiber
  • Slowing down the system clock
  • Observing crosstalk
  • Measuring operating margins
  • Observing metastable states in flip-flops

Transmission Lines

  • The quality factor, Q, and why lumped circuits can ring and cause EMI
  • Infinite uniform transmission line
  • Effects of source and load impedance
  • Special transmission line cases
  • Determining line impedance and propagation delay using TDR and VNA
  • Skin/proximity effect and dielectric loss
  • The capacitive load: ZO and propagation delay
  • Matching ZO with trace alturations (neckdowns): minimizing the C load
  • 90° and 45° bends: are they concerns?
  • Characteristics of T lines: coax, pair, micro strip, buried micro strip, stripline, and differential: asymmetric, dual, and edge
  • Even/odd and differential/common modes and their effects on LVDS

Terminations

  • End/source/middle terminators
  • AC biasing for end terminators: where should it be used and how to choose the capacitor
  • Hairball networks, bifurcated lines, and capactive stubs
  • Terminating differentials: eliminating common mode and minimizing power
  • What causes differentials unbalance?
  • Diode and active terminators, resistor selection, and crosstalk in terminators

Vias

  • Mechanical properties of vias
  • Capacitance and inductance of vias
  • Return current and its relation to vias
  • Through hole, blind, buried, and micro vias
  • Intelligent vias and autorouters
  • Via discontinuity and via resonance concerns

Ground Planes and Layer Stacking

  • High-speed current follows the path of least inductance
  • Crosstalk in solid and slotted ground planes
  • Inductive/capacitive ratios for micro strips, striplines, and asymmetric, dual, and edge LVDS
  • Guard traces: do they stop crosstalk and can they resonate?
  • Near-end and far-end crosstalk
  • Separating analog from ECL/PECL, and TTL/CMOS the concept of moats/floats/drawbridge
  • Split planes: CMOS/TTL, PECL, and analog using the same bias voltages
  • How to stack printed circuit board layers (e.g., 4, 6, and 10 layer) for ZO and crosstalk control, Cu fills on signal layers, and minimizing warpage
  • Interplane capacitance: how thin, what material, and stackup placement
  • SIR vs. frequency, software for performing crosstalk and ground bounce tests

Bypassing and Power Delivery

  • Providing a stable voltage reference: Cu planes
  • Distributing uniform voltage: sense lines, bulk C, and interplane C
  • Choosing a bypass capacitor: electrolytic/tantalum and ceramic
  • Power plane resonance: serial and parallel; how to minimize both
  • Designing a .1 ohm bypass system up to Fknee
  • Designing for constant ESR. IC die capacitance; discrete C in the IC package
  • Why the 0201–both for better bypassing and EMI control
  • Minimizing L-capacitor layouts for SOICs, PLCCs, and various configurations of BGAs

Connectors and Cables

  • Mutual and series inductance: how connectors create crosstalk and EMI
  • Using connectors on a multidrop bus (Z mismatch reflection) and how to match ZC to ZO
  • Measuring coupling in a connector
  • Continuity of Gnd underneath a connector
  • Special connectors for high-speed requirements: crosstalk and matching ZO
  • Differential signaling through a connector

Buses

  • Multidrop systems: drivers, transceivers, and RAMBUS
  • How they function, clock rates, and typical failures
  • ISI: minimize the effect with equalization and preemphasis
  • LVDS: types, unbalance, noise, layout, and making them function
  • Bus speed up methods: distributive driving and load capacitance matching

Clock Distribution

  • Timing margin and clock skew
  • Using low-impedance drivers and clock distribution lines
  • Source termination of multiple clock lines
  • Controlling crosstalk on clock lines
  • Delay adjustments: serpentine traces/DACs and varisters for dynamic delay
  • Differential distribution
  • Controlling clock signal duty cycle using the integrator
  • Source synchronous clocking, DDR, and RDRA

For more information contact the Short Course Program Office:
shortcourses@uclaextension.edu | (310) 825-3344 | fax (310) 206-2815

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