Low-Density Parity-Check (LDPC) Codes
This course covers representation via bipartite graphs, message-passing decoding algorithms, code design algorithms, stopping sets, graph-conditioning techniques for error-floor reduction, and supporting multiple rates with a unified structure. Additional topics include LDPC codes as universal codes, decoding algorithms based on belief, propagation/message-passing, LDPC codes as IRA codes and extended IRA codes, LDPC codes based on finite geometries (cyclic and quasi-cyclic), array codes as LDPC codes, LDPC code design techniques using EXIT charts, performance of LDPC codes in the 802.11n MIMO OFDM Channel, Protograph LDPC codes, Accumulate Repeat Accumulate (ARA) protograph family of codes, LDPC codes with linear minimum distance, Protograph LDPC code constructions using Approximate Cycle Extrinsic Message Degree (ACE), FPGA implementation of a universal bipartite graph decoder, and higher parallelization and throughput via protograph based decoding implementations.
Participants may take this course in combination with Introduction to Error-Control Coding or Ultra-Wideband System Design.
Lecture notes are distributed on the first day of the course. These notes are for participants only and are not for sale.
Coordinator and Lecturer
Richard D. Wesel, PhD, Associate Dean, Academic and Student Affairs, and Professor, Department of Electrical Engineering, Henry Samueli School of Engineering and Applied Science, UCLA. Since 1996, Dr. Wesel has been on the UCLA faculty pursuing research primarily in channel coding. Prior to this, he conducted research as a member of technical staff at AT&T Bell Labs. He holds four patents and has authored 100 conference and journal papers. Dr. Wesel received a National Science Foundation CAREER Award to pursue research on robust and rate-compatible coded modulation, and received an Okawa Foundation Award and the TRW Excellence in Teaching Award from the UCLA Henry Samueli School of Engineering and Applied Science. He is a Senior Member of the IEEE. He has served as chair of the Communications Major Field in the UCLA Department of Electrical Engineering and as an associate editor for the IEEE Transactions on Communications in the area of coding and coded modulation.
Dariush Divsalar, PhD, Principal Scientist, Jet Propulsion Laboratory, California Institute of Technology, Pasadena. During the past 20 years, Dr. Divsalar has taught graduate courses at UCLA and Caltech. He has published over 150 papers, coauthored three books, and holds 10 U.S. patents. Recently, one of his papers was selected as one of the key research papers published by the IEEE Communications Society in the past five decades. He has received over 25 NASA Tech Brief awards and a NASA Exceptional Engineering Achievement Medal, and served as editor of IEEE Transactions on Communications from 1989 to 1996. Dr. Divsalar is a Fellow of IEEE.
Christopher R. Jones, PhD (BS, MS, and PhD, Electrical Engineering, UCLA, 1995, 1996, and 2003 respectively). Since 2004 Dr. Jones has been with the Jet Propulsion Laboratory, Pasadena, California, where his technical focus has been on the design and implementation of low-density parity-check-based FEC systems. From 1997 to 2002 he was with the Broadcom Corporation, Irvine, California. Dr. Jones has patents and publications in topics including cable modem, VDSL, direct broadcast satellite, turbo coding, and low-density parity-check coding.
William E. Ryan, PhD, Professor, Electrical and Computer Engineering Department, University of Arizona, Tucson. Dr. Ryan’s research interests involve coding and signal processing for data transmission and storage. Prior to his current position, he held positions at The Analytic Sciences Corporation, Ampex Corporation, and Applied Signal Technology. From 1993 to 1998, he was with the Electrical and Computer Engineering Department faculty at New Mexico State University, Las Cruces. He is a Senior Member of the IEEE and was an associate editor for the IEEE Transactions on Communications for modulation, coding, and equalization from 1998-2005.
Stephan ten Brink, PhD, Director, Wireless Baseband, Wionics Research – Realtek Group, Irvine, California. Dr. ten Brink joined Wionics Research – Realtek Group in 2003. Wionics designed and brought to mass production the first single-chip MAC/PHY CMOS solution for WiMedia UWB. From 2000 to June 2003 he was a member of technical staff in the Wireless Research Lab, Bell Laboratories, Lucent Technologies, Holmdel, New Jersey, conducting research on channel coding schemes for multiple antenna systems. In 2003 he received the Vodafone innovation award for contributions to wireless modem design. In 2004 he was a co-recipient of the IEEE Stephen O. Rice paper prize for contributions to error correcting coding for multiple antenna channels. His interests are in the field of channel coding, multiple antenna communications, and cognitive radio. Dr. ten Brink received the Dipl.-Ing. and Dr.-Ing in Electrical Engineering from the University of Stuttgart, Germany, in 1997 and 2000, respectively.
Andres I. Vila Casado, PhD, Department of Electrical Engineering, Henry Samueli School of Engineering and Applied Science, UCLA. Since 2003 Dr. Vila Casado has been working with Professor Richard Wesel in various channel-coding topics, such as LDPC code design and decoding, turbo-codes, and multiple-access techniques. In particular, he developed the informed dynamic scheduling decoder for LDPC codes, which he presents as part of this course. From 2002-2003 he conducted research as a member of Dr. Sergio Benedetto’s channel-coding group at the Politecnico di Torino, Italy. Dr. Vila Casado received his BS degree from Politecnico di Torino in 2002 and MS and PhD degrees from UCLA in 2004 and 2007, respectively.
Introduction to Low-Density Parity-Check Codes
- Message-passing decoder using probabilities
- Example of erasure correction
- Stopping sets and related design algorithms
- Enforcing a desired rate during density evolution
- Supporting multiple rates with a unified structure
- LDPC codes as universal codes
LDPC Codes–Representations and Algorithms
- Low-density parity check (LDPC) codes
— Representation via bipartite graphs
— Code design algorithms and encoding
- Iterative LLR decoding of LDPC codes on the AWGN channel
— Belief propagation/message passing decoding via graphical representations
— Various equivalent or near-equivalent algorithms (min sum, sum product, etc.)
— Detailed decoding examples
— Performance results (AWGN channels, burst noise channels, ISI channels, etc.)
- Structured IRA codes
- Universality and fading channels
- Generalized LDPC codes
- Finite geometry codes and RS-based LDPC codes
Decoding LDPC Codes–Scheduling and Trapping Sets (Vila Casado)
- Effects of message-passing scheduling in LDPC decoding performance
— Flooding schedules
— Sequential schedules
— Dynamic schedules
- Informed dynamic Scheduling (IDS) for LDPC decoders
- Complexity and implementability of IDS
- Performance of IDS on trapping sets
Low-Density Parity-Check Codes–continued (ten Brink, Divsalar, and Jones)
- LDPC design using EXIT charts
- Code design for arbitrary channel interfaces (MIMO/ISI/watermarking channels)
- Performance of LDPC codes in 802.11n MIMO OFDM channels
- Protograph LDPC codes
- Accumulate Repeat Accumulate (ARA) protograph family of codes
- Protograph codes construction with linear minimum distance using weight enumerators
- Encoders for Protograph LDPC codes
- Protograph code constructions using Approximate Cycle Extrinsic Message Degree (ACE)
- Hardware implementations
— Universal bipartite graph decoder
— Protograph decoding
— Quasi-cyclic encoding
For more information contact the Short Course Program Office:
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