Gain an academic curriculum in the subject of automatic testing of electronics for test engineers. Explore the many changes of the automatic testing paradigm in the past decade and how today’s test engineering professionals has taken on a number of new roles.
Learn the design and construction of ATE and in many cases the test engineer in fact designs his/her ATE. The design consists of bringing together instruments from bus standards such as PXI, VXI, LXI, AXIe, and IEEE-488. This course requires understanding of software such as instrument drivers, test executives and graphical user interface (GUI) programs such as LabVIEW, Agilent VEE and others. Additionally, the test engineer building an ATE should have a good understanding of measurements, accuracies, precision and environmental conditions affecting the ATE. Design of interfaces and test fixtures is also discussed. The course explores other types of automatic test, including, IC ATEs, in-circuit ATEs, manufacturing defects analyzers, automatic optical inspection (AOI), x-ray inspection, and thermal imaging.
While the test engineer has an important role to play in the ATE design, construction and integration, the field of test engineering centers around the concept of test designs. Usually called test program development, the test engineer creates test procedures that determines:
- whether the unit under test (UUT) passes all the tests,
- that passing of tests provides a sufficient test coverage or confidence that a passing UUT works properly, and
- the root cause of a failure and provide unambiguous repair instructions
In order to achieve these requirements the test engineer needs to thoroughly understand the UUT’s functions, its specifications, its failure modes and to utilize this information to create a test strategy that will provide a comprehensive, yet efficient test. This course teaches test engineers how to accomplish this in an efficient and cost-effective manner.
This course requires an understanding of: basic digital and analog circuit elements; design for testability techniques; IEEE-1149.1 (JTAG) boundary scan; and other scan techniques. Design for Testability (DFT) and for Built-in Self Test (BIST), a UCLA Extension course taught during the same week prior to this course, provides the necessary background.
Participants receive lecture notes on the first day of the course. These notes are for participants only and are not on sale.
Coordinator and Lecturer
Louis Y. Ungar, President of Advanced Test Engineering (A.T.E.) Solutions, Inc. El Segundo, CA. As a test engineer, Mr. Ungar designed automatic test equipment (ATE), created hundreds of test programs for dozens of ATEs. As a design engineer he designed payload systems for the Space Shuttle, eventually leading a team of designers. With both engineering and management experience in test and design, Mr. Ungar founded A.T.E. Solutions, Inc. in 1984, a highly respected test and testability consulting and educational firm.
Mr. Ungar serves as Testability Committee Chair for the Surface Mount Technology Association (SMTA), as Consultant to the American Society of Test Engineers (ASTE), the founding President of the Testability Management Action Group (TMAG) and various test and testability groups of the Institute of Electrical and Electronics Engineers (IEEE). He has recently balloted on the IEEE-1149.1-2013 and the IEEE-P1687. He can be reached at LouisUngar@ieee.org.
For more information contact the Short Course Program Office:
firstname.lastname@example.org (310) 825-3344 | fax (310) 206-2815